Semiconductor devices are designed for higher capacity and low power use all the while operating at higher speeds. Particularly, the frequencies of signals transmitted and received for high speed operations have greatly increased. However, increased signal frequencies lead to reduced noise tolerance and unwanted signal reflection due to impedance mismatching. An impedance matching circuit provided in a semiconductor device is known as an on-die termination circuit.
FIG. 1 shows a conventional on-die termination circuit.
As shown in FIG. 1, the conventional on-die termination circuit includes a pad DQPAD1, an external resistor R1, a comparator 1, a counter 2, and a driver 3.
The pad DQPAD1 serves as a data input/output pad through which data is inputted and outputted. The external resistor R1 is coupled to one side of the pad DQPAD1.
The comparator 1 compares the pad voltage VPAD1 with the reference voltage VREF1 to generate a comparison signal COM1. For example, when the pad voltage VPAD1 is higher than the reference voltage VREF1, the comparator 1 outputs a high-level comparison signal COM1. When the pad voltage VPAD1 is lower than the reference voltage VREF1, the comparator 1 outputs a low-level comparison signal COM1. The reference voltage VREF1 corresponds to a level of the pad voltage VPAD1 measured when a resistance value of the external resistor R1 is substantially equal to the resistance value of the driver 3. As shown in FIG. 2, the comparator 1 includes a differential amplifier which includes two NMOS transistors N1, N2 and two PMOS transistors P4, P5, wherein each of the NMOS transistors N1, N2 receive a pad voltage VPAD1 and a reference voltage VREF1, and the PMOS transistors P4, P5 operate as a constant current source.
The counter 2 outputs a 3-bit driving signals DRVP in response to the comparison signal COM1. That is, when the comparison signal COM1 is at a high level, the counter 2 up-counts the driving signals DRVP by one bit to increase bit values of the driving signals DRVP. However, when the comparison signal COM1 is at a low level, the counter 2 down-counts the driving signals DRVP by one bit to reduce the bit values of the driving signals DRVP. The counter 2 includes a general 3-bit counter circuit.
The driver 3 drives the pad DQPAD1 in response to the 3-bit driving signals DRVP.
Such a conventional on-die termination circuit as above compares the level of the pad voltage VPAD1 with the level of the reference voltage VREF1 by using the comparator 1, changes the resistance value of the driver 3 according to the comparison result, and allows the resistance value of the external resistor R1 to be substantially equal to the resistance value of the driver 3.
Among the transistors N1, N2, P4, P5 in the comparator 1 as shown in FIG. 2, the two PMOS transistors P4, P5 must be manufactured in the same size because they operate as the constant current source. However, due to characteristics of a manufacturing process, for example, a difference in the distribution of etching plasma, a difference in the distribution of source power (power applied to pull the etching plasma in the wafer direction) and the like, since the two PMOS transistors P4, P5 are not manufactured in the same size, they may not operate as the constant current source.
Therefore, the comparator 1 generates an offset voltage at a predetermined level even after the impedance matching operation is completed. That is, when the level of the pad voltage VPAD1 is substantially equal to the level of the reference voltage VREF1, the offset voltage of the comparator 1 may be zero. However, when the sizes of the two PMOS transistors P4, P5 are different from each other, the offset voltage of the comparator 1 has a predetermined level other than zero even if the levels of the pad voltage VPAD1 and the reference voltage VREF1 are substantially equal to each other.
Thus, even after the impedance matching operation is completed, the comparator 1 generates the high or low-comparison signal COM1 in order to operate the counter 2, so that the resistance value of the driver 3 is changed by the counter 2. As a result, since the resistance values of the driver 3 and the external resistors R1 are different from each other, signal reflection may not be reduced.